Vista - CPU L2 Cache Memory setting in Vista

Hi Sale666,

Yep, as Johngalt posted, you would use 2048 KB (2MB)----800 (hex) in step 6.

Shawn

Shawn, I believe you mis-understand what is being expressed when Intel says 2 x 4096.

Basically, all but the most recent (Yorkfield) Quad-core Intel chips are basically a pair of dual-core chips glued together. Their L2 caches are completely seperated. Cores 0 and 1 access L2 cache A, and Cores 2 and 3 access L2 cache B. In no way can Core 0 directly access cache B. It might be helpful to think of a Quad-core machine as a dual-processor dual-core machine.

That registry setting is telling Windows how much L2 cache can be accessed per core. This is a per-processor setting! Not a global sum of the total L2 cache. And, when I say "per-processor," it's important to think of that in the old single-core usage of the term. In modern parlance, that registry value is for the amount of L2 accessible per core.

Thus, the proper value is the maximum amount of cache that each core can address, which, in this quad-core Intel example, is 4096 kbytes. (Even though 2 cores actually share that 4096 kbytes.) The correct registry setting is '1000'.

For AMD systems that report 2 x 512 kbytes, the correct setting would be '400,' as each core has its own completely seperate L2 cache.

The newest Intel quad-core chips have a unified L2 cache. For these processors, you would use that simple value, as all cores access the same L2 cache.

To my knowledge, AMD is still producing chips with seperate L2 caches. However, their latest chips have a unified L3 cache.. but there is no registry tweak for an L3 cache that I am aware of.

-ltwally

Thank you Itwally.

I updated the tutorial to use another method of finding out the correct L2 cache size to use as reported from HAL to make it easier for everyone.

Shawn

No problem. I've always been curious if this value has any odd performance penalties for Core2Duo processors, what with the way the cores are actually sharing that L2 cache. Unfortunately, you'd probably have to find a Windows Kernel engineer to give you the answer.

Itwally,

Mine is reported as 2x6144 in CPU-Z and as 6144 in the System Health Report (from HAL). So it seems that even though my Core 2 Quad Q9450 says it has a 12MB L2, it actually is being reported as having 6144 per core by HAL. I have not seen any performance hit so far with the setting as 6144 vs 12288. It would be rare for Vista to not get the size from HAL and have to resort to this registry setting anyway though.

What the HAL is (correctly) detecting is that you have 6megs of L2 cache per core. Now, the HAL is not intelligent enough to realize that cores 0 & 1 are actually sharing the same L2 cache, and ditto with cores 2 & 3.

Your processor looks something like this:
Whereas the classic model that was used at the time the Windows kernel was engineered looked a lot more like this

I have a laptop with Core2Duo T9300 processor stated that it has 6MB L2 cache. From the tutorial, that processor is stated to have 12MB L2 cache but then it is set to 6MB L2 cache in Vista, may I know why is that ? Also since my T9300 has 6MB L2 cache, should I set it to 6144 then ? Thanks in advance.

Hi YongKailoon,

Welcome to Vista Forums. You will want to see what HAL is reporting in STEP ONE as the L2 size and use that size in STEP TWO.

My CPU basically has two separate dual cores (2x2 cores) with each dual core having 6MB. Together they have a total of 12MB, but HAL still registers it as 6MB being used per dual core. The top diagram posted by Itwally above can help make sense of this a bit more.

Hope this helps,
Shawn

I see, from this I can actually assume that a standard dual core processor won't show 2 x of 3MB L2 cache since it is just one processor. From that diagram you mentioned, if I understand it properly the quad core is actually two processors of dual core so it makes it quad core. Anyway, I'll double check it with HAL but I hope my assumptions are right too.

You are exactly correct.

Now that you're no longer confused, I'll go ahead and confuse you a little.

The diagram above is valid for the Intel Quad-Core chips for the past 2 years or so. The very latest version of the Intel Core2Quad chips is code-named "Yorkfield," and looks like this:
This is a much better design, as it allows all cores access to the same L2 cache - meaning they can trade data easily.

Now, to unconfuse you: the method that Brink uses will give you the correct value to use. So, just use it always.